Cellular SoC Frontend STA Engineer (m/f/d)

Description

You will be responsible for constraint development, including deliveries for synthesis, PnR, and sign-off STA. You will work on partition- as well as SoC-level and verify the results post-synthesis for all STA modes.

In this role, you will be the link between digital design, mixed-signal design (.lib definition), and physical design. Your responsibility is to achieve sign-off quality of timing constraints, based on stakeholder requirements.

Further, you will closely collaborate with digital designers to understand the design intent and its clock structure to optimize power, performance, and area. With CAD and PD teams you will continuously improve development flows.

Preferred Qualifications

• Bachelor’s or master’s degree in electrical engineering, Computer Science/Software Engineering, or equivalent with 5+ years of working experience, or a PhD in a relevant field with 3+ years of proven experience.
• A strong background in RTL design and SoC practices, such as multiple voltage and clock domains, integration of mixed-signal IPs, and power optimizations, is highly valued.
• Experience with synthesis flows and optimization techniques for power, performance, and area trade-offs, as well as logic equivalence checking or ECO implementation, is a plus.

Minimum Qualifications

• Hands-on experience on multiple projects with constraint development, analysis, and debugging.
• Proven experience with industry-standard tools for STA, e.g., PrimeTime or Tempus, including multi-mode multi-corner analysis.
• Understanding of hierarchical design approaches, timing budgeting, asynchronous interfaces, DFT implementations, as well as timing and physical convergence.
• Proficient in day-to-day usage of scripting languages (TCL, Perl, Shell, Bash, Python), Linux, and revision control systems (e.g., PerForce).
• Strong understanding of Verilog with the ability to analyse RTL/Netlist designs.
• Strong interpersonal and communication skills, as well as the ability to find effective technical solutions between RTL-Design and Physical-Design teams.
• English language proficiency is required for this position.